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Author Title Type [ Year(Desc)]
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2010
L. Suresh, Rameshan, N., Narayan, A., Zwolinski, M., Gaur, M. S., Laxmi, V., and Singh, V., “EDA Design Flow Acceleration using GPGPUs”. 2010.
N. Rameshan, Laxmi, V., Gaur, M. S., and Ahmed, M., “Minimal path, Fault Tolerant, QoS aware Routing with node and link failure in 2-D Mesh NoC”, in Defect and Fault Tolerance in VLSI Systems (DFT), 2010 IEEE 25th International Symposium on, 2010.
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