You are here

Biblio

Found 5 results
Author [ Title(Desc)] Type Year
Filters: Author is MS Gaur  [Clear All Filters]
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 
A
L. Suresh, Rameshan, N., Gaur, M. S., Zwolinski, M., and Laxmi, V., Acceleration of functional validation using gpgpu, in Electronic Design, Test and Application (DELTA), 2011 Sixth IEEE International Symposium on, 2011.
M
N. Rameshan, Laxmi, V., Gaur, M. S., and Ahmed, M., Minimal path, Fault Tolerant, QoS aware Routing with node and link failure in 2-D Mesh NoC, in Defect and Fault Tolerance in VLSI Systems (DFT), 2010 IEEE 25th International Symposium on, 2010.
Q
N. Rameshan, Biyani, A., Gaur, M. S., Laxmi, V., and Ahmed, M., Qos aware minimally adaptive XY routing for NoC, 17th International Conference on Advanced Computing and Communication (ADCOM), Bangalore, India, 2009.