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Q

N. Rameshan, Biyani, A., Gaur, M. S., Laxmi, V., and Ahmed, M., “Qos aware minimally adaptive XY routing for NoC”, 17th International Conference on Advanced Computing and Communication (ADCOM), Bangalore, India, 2009.

M

N. Rameshan, Laxmi, V., Gaur, M. S., and Ahmed, M., “Minimal path, Fault Tolerant, QoS aware Routing with node and link failure in 2-D Mesh NoC”, in Defect and Fault Tolerance in VLSI Systems (DFT), 2010 IEEE 25th International Symposium on, 2010.

I

K. Kumar Paliwal, George, J. Shaji, Rameshan, N., Laxmi, V., Gaur, M. S., Janyani, V., and Narasimhan, R., “Implementation of QOS aware Q-routing algorithm for network-on-chip”, in Contemporary Computing, Springer, 2009, pp. 370–380.

E

L. Suresh, Rameshan, N., Narayan, A., Zwolinski, M., Gaur, M. S., Laxmi, V., and Singh, V., “EDA Design Flow Acceleration using GPGPUs”. 2010.

A

L. Suresh, Rameshan, N., Gaur, M. S., Zwolinski, M., and Laxmi, V., “Acceleration of functional validation using gpgpu”, in Electronic Design, Test and Application (DELTA), 2011 Sixth IEEE International Symposium on, 2011.