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Distributed Systems Group
Universitat Politècnica de Catalunya BARCELONATECH
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Laxmi V
Year of Publication
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2010
Suresh, L., Rameshan, N., Narayan, A., Zwolinski, M., MS, G., , & Singh, V. (2010).
EDA Design Flow Acceleration using GPGPUs
.
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Rameshan, N., , MS, G., & Ahmed, M. (2010).
Minimal path, Fault Tolerant, QoS aware Routing with node and link failure in 2-D Mesh NoC
. Presented at the. IEEE.
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