Suresh, L., Rameshan, N., MS, G., Zwolinski, M., & Laxmi, V. (2011). Acceleration of functional validation using gpgpu. Presented at the. IEEE.

Suresh, L., Rameshan, N., Narayan, A., Zwolinski, M., MS, G., , & Singh, V. (2010). EDA Design Flow Acceleration using GPGPUs.

Rameshan, N., , MS, G., & Ahmed, M. (2010). Minimal path, Fault Tolerant, QoS aware Routing with node and link failure in 2-D Mesh NoC. Presented at the. IEEE.

Paliwal, K. K., George, J. S., Rameshan, N., Laxmi, V., MS, G., Janyani, V., & Narasimhan, R. (2009). Implementation of QOS aware Q-routing algorithm for network-on-chip. Springer.

Rameshan, N., Biyani, A., MS, G., Laxmi, V., & Ahmed, M. (2009). Qos aware minimally adaptive XY routing for NoC. 17th International Conference on Advanced Computing and Communication (ADCOM), Bangalore, India.