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Found 5 results
Author Title [ Type(Desc)] Year
Filters: Author is Mateo Valero  [Clear All Filters]
Conference Paper
M. March, García, J., Cerdà-Alabern, L., Corbal, J., and Valero, M., Analysis of a High Performance DRAM/SRAM Memory Scheme for Fast Packet Buffers, in Proc. of the First Workshop on Productivity and Performance in High-End Computing (WEPA-1), in conjunction with HPCA-10, Madrid, Spain, 2004.
J. García, Corbal, J., Cerdà-Alabern, L., and Valero, M., Design and Implementation of High-Performance Memory Systems for Future Packet Buffers, in Proc. of the 36th Annual International Symposium on Microarchitecture (MICRO'36), San Diego, California, USA, 2003, pp. 373–384.
J. García, March, M., Cerdà-Alabern, L., Corbal, J., and Valero, M., On the Design of Hybrid DRAM/SRAM Memory Schemes for Fast Packet Buffers, in Proc. of the IEEE High Performance Switching and Routing (HPSR), Phoenix, Arizona, USA, 2004, pp. 15–19.
Journal Article
J. García, March, M., Cerdà-Alabern, L., Corbal, J., and Valero, M., A DRAM/SRAM Memory Scheme for Fast Packet Buffers, IEEE Transactions on Computers, vol. 55, pp. 588–602, 2006.